Integrated circuits (ICs) are typically manufactured with external connections for receiving either power supply voltages, control or communication signals with external devices or systems. The trend in fabricating ICs is to increase the density of internal components, such as transistors and interconnects. In addition, the power supply potential used to operate the integrated circuits continues to decrease.
As integrated circuit devices increase in density and operating supply voltages decrease, the integrated circuits become more sensitive to the effects of electrostatic discharge. Electrostatic discharge (ESD) refers to the phenomenon of electrical discharge of high current for a short time duration resulting from a build up of static charge on a particular integrated circuit package, or on a nearby human handling that particular IC package. ESD is a serious problem for semiconductor devices since it has the potential to destroy an entire IC. Because ESD events occur often across the silicon circuits attached to IC package terminals, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits.
One solution is the use of a grounded gate transistor as a simple ESD protection circuit. The transistor is configured as a diode and has a drain junction breakdown voltage lower than the gate dielectric breakdown voltage. While this circuit provides some protection from ESD events, an ESD protection circuit should be able to protect an IC against static discharge by non-destructively passing large currents through a low impedance path in a short time.
As power supply voltages scale down (e.g., from 5.0 volts, to 3.3 volts, to 2.5, 1.8, 1.3 volts and below), backward compatibility with the higher voltage requirements of older ICs may be desirable. Accordingly, an electrostatic discharge (ESD) clamp circuit employing stacked p-type metal oxide semiconductor (PMOS) transistors may be used. The high voltage clamp may have series coupled transistors which form a switchable conductive circuit between a high voltage supply and ground. These transistors may be turned off during non-ESD events, but activated during an ESD event to provide a discharge path for an ESD current. However, the gates of these discharge transistors may not be driven fully to ground, and thus, the transistors may not dissipate the maximum possible current from the supply node.
For the reasons stated above, there is a need in the art for a circuit which increases the efficiency of ESD power supply clamping circuitry to sink larger currents during an ESD event, while maintaining backward compatibility with the higher voltage requirements of older ICs.